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Zen (microarchitecture) : ウィキペディア英語版
Zen (microarchitecture)

| application = Desktop, Laptop, Server
| core1 =
| TDP =
}}
Zen is an upcoming CPU microarchitecture created by AMD, expected for release in October 2016.
==Architecture==
According to AMD, Zen's main focus will be on increasing per-core performance rather than core count or multi-threading performance.〔(【引用サイトリンク】title=Weekend tech reading: AMD 'Zen' and their return to high-end CPUs, tracking Windows pirates - TechSpot )〕〔(【引用サイトリンク】title=AMD: Zen chips headed to desktops, servers in 2016 - The Tech Report - Page 1 )〕 Reports from AMD indicate that Zen will abandon modular CMT (Clustered Multithread) for a SMT (Simultaneous Multithreading) microarchitecture,〔〔(【引用サイトリンク】url=http://www.expreview.com/33161.html )〕 which is the same model that Intel uses, as well as what AMD has used in past architectures. Adapting their chips from the less-popular CMT to SMT〔 is expected to offer much higher number threading efficiency, but also possibly increase the die size of a Zen module.〔
Reportedly, the Zen architecture will be built on a more efficient 14 nanometer process, rather than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.〔 The "Summit Ridge" Zen family will also feature a unified AM4 socket with its GPU-equipped "Raven Ridge" APU counterparts,〔(【引用サイトリンク】title=AMD's next-gen Zen CPU due in 2016 - PC Gamer )〕 and feature DDR4 support and a 95W TDP. Zen does not support DDR3; only 7th generation AMD APUs (also fitting the AMD AM4 unified socket) support DDR3 and DDR4. While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15W and 15 to 35W for performance-oriented mobile products with up to four Zen cores.
Zen will support RDSEED.
Zen core will have four integer units, two address generation units and four floating point units, and the decoder can decode four instructions per clock cycle.
L1 cache size is 32 kiB and L2 cache size 512 kiB per core. Two of the floating point units are adders, two are multipliers.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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